Implantable stimulation devices deliver electrical stimuli to nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder subluxation, etc. The description that follows will generally focus on the use of the invention within a Spinal Cord Stimulation (SCS) system, such as that disclosed in U.S. Pat. No. 6,516,227. However, the present invention may find applicability with any implantable medical device or in any implantable medical device system.
An SCS system typically includes an Implantable Pulse Generator (IPG) 10 shown in plan and cross-sectional views in FIGS. 1A and 1B. The IPG 10 includes a biocompatible device case 30 that holds the circuitry and battery 36 necessary for the IPG to function. The IPG 10 is coupled to electrodes 16 via one or more electrode leads 14 that form an electrode array 12. The electrodes 16 are configured to contact a patient's tissue and are carried on a flexible body 18, which also houses the individual lead wires 20 coupled to each electrode 16. The lead wires 20 are also coupled to proximal contacts 22, which are insertable into lead connectors 24 fixed in a header 28 on the IPG 10, which header can comprise an epoxy for example. Once inserted, the proximal contacts 22 connect to header contacts 26, which are in turn coupled by feedthrough pins 34 through a case feedthrough 32 to circuitry within the case 30.
In the illustrated IPG 10, there are thirty-two lead electrodes (E1-E32) split between four leads 14, with the header 28 containing a 2×2 array of lead connectors 24. However, the number of leads and electrodes in an IPG is application specific and therefore can vary. In a SCS application, the electrode leads 14 are typically implanted proximate to the dura in a patient's spinal cord, and when a four-lead IPG 10 is used, these leads are usually split with two on each of the right and left sides of the dura. The proximal electrodes 22 are tunneled through the patient's tissue to a distant location such as the buttocks where the IPG case 30 is implanted, at which point they are coupled to the lead connectors 24. A four-lead IPG 10 can also be used for Deep Brain Stimulation (DBS) in another example. In other IPG examples designed for implantation directly at a site requiring stimulation, the IPG can be lead-less, having electrodes 16 instead appearing on the body of the IPG for contacting the patient's tissue.
As shown in the cross section of FIG. 1B, the IPG 10 includes a printed circuit board (PCB) 40. Electrically coupled to the PCB 40 are the battery 36, which in this example is rechargeable; other circuitry 50a and 50b coupled to top and bottom surfaces of the PCB; a telemetry coil 42 for wirelessly communicating with an external controller (not shown); a charging coil 44 for wirelessly receiving a magnetic charging field from an external charger 90 (FIG. 2) for recharging the battery 36; and the feedthrough pins 34 (connection not shown). If battery 36 is permanent and not rechargeable, charging coil 44 would be unnecessary. (Further details concerning operation of the coils 42 and 44 and the external devices with which they communicate can be found in U.S. Patent Application Ser. No. 61/877,871, filed Sep. 13, 2013).
Battery management circuitry 84 for the rechargeable battery 36 in the IPG 10 is described in one example in commonly-owned U.S. Patent Application Publication 2013/0023943, which is incorporated herein by reference in its entirety, and shown in FIG. 2. Rechargeable battery 36 may comprise a Li-ion polymer battery, which when fully charged can provide a voltage (Vbat=Vmax) of about 4.2 Volts. However, other rechargeable battery chemistries could be used for battery 36 as well.
An external charger 90, typically a hand-held, battery-powered device, produces a magnetic non-data modulated charging field 98 (e.g., 80 kHz) from a coil 92. The magnetic field 98 is met in the IPG 10 by front-end charging circuitry 96, where it energizes the charging coil 44 by inducing a current in the coil. The induced current is processed by rectifier circuitry 46, including a rectifier and optionally a filtering capacitor and a voltage-magnitude-limiting Zener diode, e.g., to 5.5V), to establish a voltage V1 (e.g., ≦5.5V), which voltage is passed through a back-flow-prevention diode 48 to produce a DC voltage, Vdc. Transistors 102 coupled to the charging coil 44 can be controlled by the IPG 10 (via control signal LSK) to transmit data back to the external charger 90 during production of the magnetic field 98 via Load Shift Keying, as is well known.
Vdc is provided to battery management circuitry 84, which may reside on an Application Specific Integrated Circuit (ASIC) along with other circuitry necessary for IPG 10 operation, including current generation circuitry (used to provide specified currents to selected ones of the electrodes 16); telemetry circuitry (for modulating and demodulating data associated with telemetry coil 42 of FIG. 1B); various measurement and generator circuits; system memory; etc. The front-end charging circuitry 96 and the battery 36 typically comprise off-chip (off-ASIC) components, along with other electronics in the IPG 10, such as the telemetry coil 42; various DC-blocking capacitors coupled to the electrodes 16 (not shown); a microcontroller 100, which can communicate with the ASIC (and the battery management circuitry 84) via a digital bus 88; and other components of lesser relevance here. Microcontroller 100 may comprise in one example Part Number MSP430, manufactured by Texas Instruments, which is described in data sheets at http://www.ti.com/lsds/ti/microcontroller/16-bit_msp430/overview.page?DCMP=MCU_other& HQS=msp430, which is incorporated herein by reference. The ASIC may be as described in U.S. Patent Application Publication 2012/0095529, which is also incorporated herein by reference.
The battery management circuitry 84 in FIG. 2 is comprised of two circuit blocks: charging circuitry 80 for generating a current for charging the battery 36, and load isolation circuitry 82 for controllably connecting or disconnecting the battery 36 from the load 75 that the battery 36 powers during normal operation of the IPG 10. Load 75 can comprise both on-chip (on-ASIC) circuit blocks such as the current generation circuitry and the telemetry circuitry mentioned earlier, and off-chip (off-ASIC) components such as the microcontroller 100.
As depicted, the charging circuitry 80, the load isolation circuitry 82, and the battery 36 generally have a T-shaped topology, with the charging circuitry 80 intervening between front-end charging circuitry 96 (Vdc) and the positive terminal (Vbat) of the battery 36, and with the load isolation circuitry 82 intervening between Vbat and the load 75.
The load isolation circuitry 82 can prohibit the battery 36 (Vbat) from being passed to power the load (Vload) dependent on a number of conditions. For example, if the load 75 is drawing a significantly high current (as indicated by overcurrent detection circuitry 74 via assertion of control signal OI), or if Vbat is too low (as indicated by undervoltage detection circuitry 70 via assertion of control signal UV), or if an external magnetic field signal μ is indicated by a Reed switch 78 (e.g., in an emergency condition warranting presentation by the patient of an external shut-off magnet), the load 75 will be decoupled from Vbat via switches 62 or 64, as assisted by OR gate 76. Discharge circuitry 68 is also provided to intentionally drain the battery 36 if Vbat is too high.
Of greater relevance to the present disclosure is the charging circuitry 80, which begins at Vdc—the DC-voltage produced by the front-end charging circuitry 96 in response to the external charger 90's magnetic field 98. Vdc splits into two paths in the charging circuitry 80 that are connected in parallel between Vdc and Vbat: a trickle charging path, and an active charging path, either of which can be used to provide a charging current (Ibat) to the battery 36 (Vbat).
The trickle charging path is passive, i.e., its operation is not controlled by control signals, and requires no power other than that provided by Vdc to produce a charging current (Itrickle) for the battery 36. As shown, the trickle charging path presents Vdc to a current-limiting resistor 50 and one or more diodes 52, and is used to provide a small charging current, Itrickle, to the battery 36. Using a small trickle charging current is particularly useful when the battery 36 is significantly depleted, i.e., if Vbat is below a threshold Vt1, such as 2.7V for example.
To produce Itrickle, Vdc must be higher than the sum of the voltage drops across the resistor 50 and diode(s) 52 and the voltage of the battery 36, Vbat. Under typical conditions and assuming three diodes 52 and a 200-ohm resistor 50 are used, the drop across the resistor 50 and diode(s) 52 will be about 2.0 Volts. Therefore, Itrickle will passively flow into the battery 36 if Vdc is greater than about 2.0V+Vbat. If this condition is not met—which would indicate that Vdc is too small (perhaps because the coupling between the external charger 90 and the IPG 10 is poor), or that Vbat is too high (which may occur as the battery 36 is gradually charged)—diodes 52 will prevent the battery 36 from draining backwards through the trickle charging path. Itrickle is generally on the order of ten milliamps. This is desirably small, because a significantly depleted rechargeable battery 36 can be damaged if it receives charging currents (Ibat) that are too high, as is well known.
The active charging path proceeds in FIG. 2 from Vdc to the battery 36 through a current/voltage source 56, which is used to produce charging current Iactive. In the example of FIG. 2, the active charging path also passes through control and protective measures of the battery management circuitry, including a charging current sense resistor 58 used in conjunction with a charging current detector 72, and an overvoltage protection switch 60 used in conjunction with an overvoltage detector 66 to open circuit the active charging path if the battery voltage, Vbat, exceeds a maximum value (such as Vmax=4.2V).
Circuitry for the current/voltage source 56 in the active charging path is shown in FIG. 3A. As its name implies, source 56 can be controlled to provide either a constant current or a constant voltage to the battery 36 during active charging. The source 56 comprises a current mirror comprised of P-channel transistors 104 and 106, which is powered by Vdc and receives a reference current, Iref, provided by reference current generator circuitry 113. Current mirror control transistor 104 mirrors a representation of Iref in current mirror output transistor(s) 106 to produce the active charging current, Iactive. In the example shown, M output transistors 106 are wired in parallel, and thus the current provided by output transistor(s) 106 equals Iactive=M*Iref. A single wider output transistor 106 (M times wider than the current mirror control transistor 104) could also be used.
The reference current generator circuitry 113 used to produce Iref is adjustable via control signals Itrim[2:0], and also comprises a current mirror. As shown, a system reference current, I′ (e.g., 100 nA), is mirrored transistors 116, 118, and 120, each of which are coupled in series to gating transistors controlled by the Itrim control signals. Transistors 116, 118, and 120 are preferably of different widths, or comprise different numbers of transistors in parallel, to provide different contributions to Iref. For example, transistors 116, 118, and 120 may respectively contribute I′*N, I′*2N, and I′*4N to Iref, thus allowing Iref to vary from I′*N to I′*7N in increments of I″*N, depending on which control signals Itrim0, Itrim1, and Itrim2 are active. Additional Itrim control signals and additional current mirror output transistors (e.g., 116-120) could be used to control Iref over a wider range, and/or with smaller resolution. Adjusting Iref in this manner in turn adjusts Iactive via operation of the current mirror transistor 104 and 106 discussed above.
Control signals Itrim are issued by a source controller 86, which communicates with the microcontroller 100 by a digital bus 88, and so the microcontroller 100 can control the source controller 86 to in turn control the source 56 via Itrim and other control signals discussed further below.
The mode in which the source 56 operates to generate a charging current depends on the magnitude of the battery voltage, Vbat, which is known to the microcontroller 100. If the battery 36 is significantly depleted, i.e., Vbat<Vt1 (e.g., 2.7), the microcontroller 100 commands the source controller 86 to disable the source 56 (Ch_en=‘0’) to turn off enable transistor 108 and prevent the production of Iactive. Thus, the battery 36 in this circumstance can only be charged via the trickle charging path, and only if magnetic field 98 and Vdc are present and sufficient.
If Vbat>Vt1, but below an upper threshold Vt2 described further below (i.e., if Vt1<Vbat<Vt2), the source 56 operates in a constant current mode. In this mode, the source 56 is enabled (Ch_en=‘1’), allowing Iactive to flow in accordance with a value represented by the Itrim control signals. When source 56 operates in constant current mode, Iactive is generally on the order of 50 milliamps. A P-channel transistor 114 in the active current path is fully on in constant current mode, thus allowing Iactive to flow to the battery 36 without resistance.
If Vbat>Vt2 (e.g., 4.0 V), the source 56 operates in a constant voltage mode. Ch_en and the Itrim control signals are still asserted in this mode. Crossing of the Vt2 threshold and switching of charging modes does not in this example rely on the microcontroller 100, but is instead affected via Vbat measurement circuitry 111 in the source 56. Vbat is determined in this circuitry 111 via a high-impedance resistor ladder, which produces a voltage Va indicative of Vbat. Va and a known band-gap reference voltage, Vref, are compared at amplifier 112. When Va>Vref, indicating that Vbat>Vt2, the amplifier 112 starts to turn off transistor 114, and the source 56 operates in constant voltage mode, providing an essentially constant voltage to the positive terminal of the battery 36. As the internal cell voltage of the battery 36 increases in this mode, its internal resistance causes Iactive to fall off exponentially, until Vbat reaches a maximum value, Vmax (e.g., 4.2V). At this point, the microcontroller 100 will consider charging of the battery 36 to be complete, and will once again assert Ch_en=‘0’ to curtail further active charging. (Additionally, overvoltage switch 60 may also be opened). By contrast, when Va<Vref, indicating that Vbat<Vt2, the amplifier 112 turns on P-channel transistor 114, and the source 56 operates in constant current mode as described earlier. Voltage Va can be trimmed as necessary using control signals Vtrim to trim the resistance in the ladder, which essentially sets threshold Vt2.
FIG. 3B generally illustrates operation of the charging circuitry 80 to produce the charging current (Ibat) received by a severely depleted battery 36 (i.e., where Vbat is below an even lower threshold V(UV)=2.0V) as a function of time during a charging session, including the trickle, constant current, and constant voltage modes enabled by the charging circuitry 80 as described above. Also shown are typical values for the charging current in each of these modes, and the capacity of the battery 36 illustrated as a percentage.
The battery management circuitry 84 of FIG. 2 provides additional safeguards, such as diode(s) 54 connected between the trickle and active charging paths to prevent leakage of the battery 36 through the overvoltage switch 60, again as explained in the '943 Publication. Diode(s) 54 thus protect the battery 36 from inadvertently discharging through overvoltage switch 60, particularly at the inopportune time when Vbat is already critically low, and when it therefore might be difficult to provide a suitably high voltage to the gate of P-channel transistor 60 to turn it off.